Cadence Design Systems (CDNS)
Provides chip-design software, verification hardware, semiconductor IP, and multiphysics simulation.
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Cadence sells the digital drafting tables and test rigs used to create chips and the electronic systems around them. Long-running chip-design software still pays most of the bills, while reusable chip building blocks and simulation tools for heat, airflow and mechanics are growing faster. Artificial-intelligence helpers are being layered across the toolbox, but they are still an add-on rather than a separate business.
Item facts: FY2025 · year ended Dec 31, 2025, from filings, earnings calls and company pages.
Judgment weights, not filed revenue
The band summarizes business focus and direction. ~ marks estimates.
9 in detail · 13 more below
Core EDA — Chip Design & Verification
Cadence's main engine combines design software, error-checking software and specialized test machines. Across the whole company, contracted work stood at $8.1B in June 2026, though Cadence does not split it among product families.
Competes with Chip design and verification suite (Synopsys) · EDA design and verification portfolio (Siemens)
In plain English
This is the broad toolbox chipmakers use before a factory produces anything: programs lay out a chip, other programs hunt for mistakes, and dedicated machines rehearse how it will behave. A missed error can waste months, so customers tend to keep a trusted set of tools for years.
They pay for time-based software access, updates and expert help, while the testing machines bring larger purchases that arrive less evenly. Its job is to supply the dependable cash and customer relationships that support Cadence's newer businesses.
Digital IC Design and Signoff
Turns a chip team's logical plan into a factory-ready physical layout. It is the largest estimated slice inside the core business; watch whether new factory processes, including Intel 14A, lead customers to use more of the tool chain.
Competes with Fusion Compiler, PrimeTime and IC Validator (Synopsys) · Aprisa and Calibre (Siemens EDA)
In plain English
Start with a rough plan for what a chip should do. Cadence's programs arrange millions of tiny parts, connect them, check their speed and power use, and prepare a layout a factory can build. It is like turning a city's zoning sketch into exact streets, pipes and building lots.
Chip teams pay for access to the connected set because each step passes work to the next. Factory approval matters too: when a future manufacturing process is certified for these tools, customers can use the flow with less risk of an expensive failed production run.
Palladium Z3 and Protium X3
Specialized machines let developers test a chip and start its software before the real chip exists. More than thirty new customers bought the current generation in FY2025; limited component supply can still shift deliveries between periods.
Competes with ZeBu-200 and HAPS-200 (Synopsys) · Veloce Strato CS and Primo CS (Siemens EDA)
In plain English
Before a new chip exists, developers still need to know whether it works and whether its software will run. Palladium acts out the design in detail; Protium makes a faster early working version. Together they are a dress rehearsal before the costly factory opening.
Customers buy the systems, add more capacity as designs grow, and keep paying for maintenance plus the software that prepares and diagnoses each test. These purchases can be large and uneven, and Cadence cannot ship every planned system when component supplies are tight.
Virtuoso and Spectre Custom IC
Designs and tests chip parts that must handle real-world signals, where one-size-fits-all automation is not accurate enough. Factory-approved models keep customers anchored; memory, radio and artificial-intelligence connections support demand.
Competes with Custom Compiler, PrimeSim and StarRC (Synopsys) · Analog FastSPICE and Solido (Siemens EDA)
In plain English
Digital tools handle neat ones and zeros; these tools work on the messier edges where electricity behaves continuously. Engineers draw and test analog, memory and radio sections much as a watchmaker fits tiny gears, checking that every part behaves under changing conditions.
Customers keep paying for software access and updates because accuracy is the product. The programs rely on detailed models supplied or approved by chip factories. If those models are late or wrong, a result that looked safe on screen may fail after manufacturing.
Xcelium, Jasper and Verisium Verification
Searches for logic mistakes before a chip reaches the factory, using several kinds of software checks. More complex chips and more built-in software create extra tests; tight links to Palladium and Protium keep the workflow together.
Competes with VCS, Verdi and VC Formal (Synopsys) · Questa One (Siemens EDA)
In plain English
Finding a bad assumption after manufacturing is painfully expensive. Xcelium runs many imagined situations, Jasper proves whether certain failures can happen, and Verisium helps engineers trace the cause. Think of an inspection gate that checks every possible route through a machine before anyone builds it.
Teams pay for continuing software access because every new design creates another mountain of checks. When ordinary computers become too slow, the same work can move into Cadence's Palladium and Protium machines, making the software and hardware more valuable together.
System Design and Analysis
The smaller family reaches beyond individual chips into boards, packages, heat, airflow and mechanical motion. Sales grew 37% in FY2026 Q2; the next test is whether newly acquired mechanical tools fit naturally with Cadence's electronics base.
Competes with Ansys simulation portfolio (Synopsys) · Xpedition and Simcenter (Siemens) · SIMULIA (Dassault Systèmes)
In plain English
Here Cadence follows a design beyond the chip itself. Its programs arrange the board that holds the parts, plan the package connecting a chip to that board, and predict heat, airflow, stress and motion across the finished system.
Electronics, vehicle and aerospace teams pay to test ideas on screen before ordering physical prototypes. That saves materials and time, while Cadence gains another sale around customers it may already serve in chip design. Recent purchases broadened the toolkit into more kinds of mechanical testing.
Allegro X, OrCAD X and Integrity 3D-IC
Designs circuit boards, chip packages and the connections between them. Demand rises as chips are assembled from smaller pieces and packed closer together; watch whether resellers keep the tools accessible to smaller engineering teams.
Competes with Xpedition and HyperLynx (Siemens EDA) · CR-8000 Design Force (Zuken)
In plain English
A chip is only useful once it can connect to memory, power and the rest of a device. Allegro and OrCAD lay out the circuit board; Integrity coordinates the package and designs that combine several smaller chips. It resembles planning roads between tightly packed buildings, where every crossing affects traffic and heat.
Large customers buy software directly, while resellers carry selected tools to smaller teams. Cadence earns from design access and analysis, and the need grows when more connections must fit into less space without overheating or interfering with one another.
Multiphysics and Physical Systems Simulation
Tests heat, airflow, structures and moving parts before a physical prototype is built. Hexagon's acquired design-and-engineering tools are expected to add $160M in FY2026; trusted results and smooth integration will decide whether customers expand use.
Competes with Ansys simulation portfolio (Synopsys) · Simcenter (Siemens) · SIMULIA (Dassault Systèmes)
In plain English
Think of a wind tunnel, heat chamber and stress-testing rig rebuilt inside a computer. Clarity, Celsius, Fidelity, Optimality and BETA CAE predict how a design handles electricity, temperature, fluids and shape; MSC Nastran and Adams add structures and motion.
Vehicle, aerospace and electronics teams pay for software and hosted computing so they can reject weak designs before spending on prototypes. The acquisition opens doors to more mechanical engineers, but those users will stay only if the combined programs exchange designs cleanly and produce results they trust.
Semiconductor IP
Ready-made chip parts save customers from rebuilding common connections, memory pieces, security and processors. Revenue grew over 40% in FY2026 Q2 from a much smaller base than core design tools; delivery milestones and customer production volumes matter.
Competes with DesignWare Interface and Foundation IP (Synopsys) · SensPro and NeuPro (CEVA)
In plain English
Why redraw every door, pipe and staircase for each building? Cadence licenses reusable chip blocks that handle common jobs such as connecting parts, storing data, securing information and processing signals. Customers fit these proven modules into a larger chip instead of creating each one from scratch.
They pay for the design, updates and sometimes royalties when finished products ship. That can shorten a development schedule, but Cadence's payment still depends on the customer's program reaching agreed delivery steps and eventually making it through the factory in volume.
Core EDA — Chip Design & VerificationCadence's main engine combines design software, error-checking software and specialized test machines. Across the whole company, contracted work stood at $8.1B in June 2026, though Cadence does not split it among product families.Cadence's main engine combines design software, error-checking software and specialized test machines. Across the whole company, contracted work stood at $8.1B in June 2026, though Cadence does not split it among product families.
In plain English
This is the broad toolbox chipmakers use before a factory produces anything: programs lay out a chip, other programs hunt for mistakes, and dedicated machines rehearse how it will behave. A missed error can waste months, so customers tend to keep a trusted set of tools for years.
They pay for time-based software access, updates and expert help, while the testing machines bring larger purchases that arrive less evenly. Its job is to supply the dependable cash and customer relationships that support Cadence's newer businesses.
Competes with Chip design and verification suite (Synopsys) · EDA design and verification portfolio (Siemens)
Digital IC Design and SignoffTurns a chip team's logical plan into a factory-ready physical layout. It is the largest estimated slice inside the core business; watch whether new factory processes, including Intel 14A, lead customers to use more of the tool chain.Turns a chip team's logical plan into a factory-ready physical layout. It is the largest estimated slice inside the core business; watch whether new factory processes, including Intel 14A, lead customers to use more of the tool chain.
In plain English
Start with a rough plan for what a chip should do. Cadence's programs arrange millions of tiny parts, connect them, check their speed and power use, and prepare a layout a factory can build. It is like turning a city's zoning sketch into exact streets, pipes and building lots.
Chip teams pay for access to the connected set because each step passes work to the next. Factory approval matters too: when a future manufacturing process is certified for these tools, customers can use the flow with less risk of an expensive failed production run.
Competes with Fusion Compiler, PrimeTime and IC Validator (Synopsys) · Aprisa and Calibre (Siemens EDA)
Palladium Z3 and Protium X3Specialized machines let developers test a chip and start its software before the real chip exists. More than thirty new customers bought the current generation in FY2025; limited component supply can still shift deliveries between periods.Specialized machines let developers test a chip and start its software before the real chip exists. More than thirty new customers bought the current generation in FY2025; limited component supply can still shift deliveries between periods.
In plain English
Before a new chip exists, developers still need to know whether it works and whether its software will run. Palladium acts out the design in detail; Protium makes a faster early working version. Together they are a dress rehearsal before the costly factory opening.
Customers buy the systems, add more capacity as designs grow, and keep paying for maintenance plus the software that prepares and diagnoses each test. These purchases can be large and uneven, and Cadence cannot ship every planned system when component supplies are tight.
Competes with ZeBu-200 and HAPS-200 (Synopsys) · Veloce Strato CS and Primo CS (Siemens EDA)
Virtuoso and Spectre Custom ICDesigns and tests chip parts that must handle real-world signals, where one-size-fits-all automation is not accurate enough. Factory-approved models keep customers anchored; memory, radio and artificial-intelligence connections support demand.Designs and tests chip parts that must handle real-world signals, where one-size-fits-all automation is not accurate enough. Factory-approved models keep customers anchored; memory, radio and artificial-intelligence connections support demand.
In plain English
Digital tools handle neat ones and zeros; these tools work on the messier edges where electricity behaves continuously. Engineers draw and test analog, memory and radio sections much as a watchmaker fits tiny gears, checking that every part behaves under changing conditions.
Customers keep paying for software access and updates because accuracy is the product. The programs rely on detailed models supplied or approved by chip factories. If those models are late or wrong, a result that looked safe on screen may fail after manufacturing.
Competes with Custom Compiler, PrimeSim and StarRC (Synopsys) · Analog FastSPICE and Solido (Siemens EDA)
Xcelium, Jasper and Verisium VerificationSearches for logic mistakes before a chip reaches the factory, using several kinds of software checks. More complex chips and more built-in software create extra tests; tight links to Palladium and Protium keep the workflow together.Searches for logic mistakes before a chip reaches the factory, using several kinds of software checks. More complex chips and more built-in software create extra tests; tight links to Palladium and Protium keep the workflow together.
In plain English
Finding a bad assumption after manufacturing is painfully expensive. Xcelium runs many imagined situations, Jasper proves whether certain failures can happen, and Verisium helps engineers trace the cause. Think of an inspection gate that checks every possible route through a machine before anyone builds it.
Teams pay for continuing software access because every new design creates another mountain of checks. When ordinary computers become too slow, the same work can move into Cadence's Palladium and Protium machines, making the software and hardware more valuable together.
Competes with VCS, Verdi and VC Formal (Synopsys) · Questa One (Siemens EDA)
System Design and AnalysisThe smaller family reaches beyond individual chips into boards, packages, heat, airflow and mechanical motion. Sales grew 37% in FY2026 Q2; the next test is whether newly acquired mechanical tools fit naturally with Cadence's electronics base.The smaller family reaches beyond individual chips into boards, packages, heat, airflow and mechanical motion. Sales grew 37% in FY2026 Q2; the next test is whether newly acquired mechanical tools fit naturally with Cadence's electronics base.
In plain English
Here Cadence follows a design beyond the chip itself. Its programs arrange the board that holds the parts, plan the package connecting a chip to that board, and predict heat, airflow, stress and motion across the finished system.
Electronics, vehicle and aerospace teams pay to test ideas on screen before ordering physical prototypes. That saves materials and time, while Cadence gains another sale around customers it may already serve in chip design. Recent purchases broadened the toolkit into more kinds of mechanical testing.
Competes with Ansys simulation portfolio (Synopsys) · Xpedition and Simcenter (Siemens) · SIMULIA (Dassault Systèmes)
Allegro X, OrCAD X and Integrity 3D-ICDesigns circuit boards, chip packages and the connections between them. Demand rises as chips are assembled from smaller pieces and packed closer together; watch whether resellers keep the tools accessible to smaller engineering teams.Designs circuit boards, chip packages and the connections between them. Demand rises as chips are assembled from smaller pieces and packed closer together; watch whether resellers keep the tools accessible to smaller engineering teams.
In plain English
A chip is only useful once it can connect to memory, power and the rest of a device. Allegro and OrCAD lay out the circuit board; Integrity coordinates the package and designs that combine several smaller chips. It resembles planning roads between tightly packed buildings, where every crossing affects traffic and heat.
Large customers buy software directly, while resellers carry selected tools to smaller teams. Cadence earns from design access and analysis, and the need grows when more connections must fit into less space without overheating or interfering with one another.
Competes with Xpedition and HyperLynx (Siemens EDA) · CR-8000 Design Force (Zuken)
Multiphysics and Physical Systems SimulationTests heat, airflow, structures and moving parts before a physical prototype is built. Hexagon's acquired design-and-engineering tools are expected to add $160M in FY2026; trusted results and smooth integration will decide whether customers expand use.Tests heat, airflow, structures and moving parts before a physical prototype is built. Hexagon's acquired design-and-engineering tools are expected to add $160M in FY2026; trusted results and smooth integration will decide whether customers expand use.
In plain English
Think of a wind tunnel, heat chamber and stress-testing rig rebuilt inside a computer. Clarity, Celsius, Fidelity, Optimality and BETA CAE predict how a design handles electricity, temperature, fluids and shape; MSC Nastran and Adams add structures and motion.
Vehicle, aerospace and electronics teams pay for software and hosted computing so they can reject weak designs before spending on prototypes. The acquisition opens doors to more mechanical engineers, but those users will stay only if the combined programs exchange designs cleanly and produce results they trust.
Competes with Ansys simulation portfolio (Synopsys) · Simcenter (Siemens) · SIMULIA (Dassault Systèmes)
Semiconductor IPReady-made chip parts save customers from rebuilding common connections, memory pieces, security and processors. Revenue grew over 40% in FY2026 Q2 from a much smaller base than core design tools; delivery milestones and customer production volumes matter.Ready-made chip parts save customers from rebuilding common connections, memory pieces, security and processors. Revenue grew over 40% in FY2026 Q2 from a much smaller base than core design tools; delivery milestones and customer production volumes matter.
In plain English
Why redraw every door, pipe and staircase for each building? Cadence licenses reusable chip blocks that handle common jobs such as connecting parts, storing data, securing information and processing signals. Customers fit these proven modules into a larger chip instead of creating each one from scratch.
They pay for the design, updates and sometimes royalties when finished products ship. That can shorten a development schedule, but Cadence's payment still depends on the customer's program reaching agreed delivery steps and eventually making it through the factory in volume.
Competes with DesignWare Interface and Foundation IP (Synopsys) · SensPro and NeuPro (CEVA)
Named in filings, launches and programs
- Cadence.AI and AI Super AgentsPlatform · RampingChipStack is active; AgentStack, ViraStack, InnoStack and AuraStack are rolling out as paid helpers layered over existing tools, with early usage-based sales.
- Technology Services and Cadence CloudServiceEngineering help, training and hosted computing sit inside the product families above, supporting adoption rather than forming another lane.
- Millennium M2000 SupercomputerPlatform · RampingA high-powered computing system co-developed with NVIDIA to speed molecular and engineering simulations.
- Cadence Reality Digital Twin PlatformPlatformBuilds virtual copies of physical systems so engineers can test operating conditions before changing the real thing.
- OpenEye Scientific SoftwareProduct lineMolecular modeling and simulation software used in life-science research.
- VLAB WorksBrandAcquired technology that creates early virtual versions of hardware so embedded-software teams can begin sooner.
- Cadence ConnectionsEcosystemA partner network connecting Cadence tools with chip factories, computing providers, reusable blocks and design services.
- Intel Foundry 14A EngagementCustomer programA multiyear program adapting Cadence tools and chip blocks to Intel's future factory process; management expects most benefit in later years.
- Unnamed Two-Nanometer Foundry IP EngagementCustomer programCadence's largest reusable-chip-block engagement with that unnamed factory customer as of April 2026; the customer was not Intel.
- Unnamed Multiyear IP ContractCustomer programA customer agreement disclosed in 2024 tied payments to delivery steps and carried work into 2025; later status was not disclosed.
- Unallocated Customer CommitmentsCustomer programCustomers had made about $0.9B of June 2026 commitments they could not cancel, without yet choosing the Cadence products.
- Arm Artisan Foundation IPProduct lineAcquired basic chip parts, memory-building tools and general-purpose connections that broaden the ready-made chip-block library.
- Secure-IC Security IPProduct lineAcquired security technology now folded into Cadence's reusable chip-block portfolio.
Cadence.AI and AI Super AgentsPlatform · Ramping
ChipStack is active; AgentStack, ViraStack, InnoStack and AuraStack are rolling out as paid helpers layered over existing tools, with early usage-based sales.
Technology Services and Cadence CloudService
Engineering help, training and hosted computing sit inside the product families above, supporting adoption rather than forming another lane.
Millennium M2000 SupercomputerPlatform · Ramping
A high-powered computing system co-developed with NVIDIA to speed molecular and engineering simulations.
Cadence Reality Digital Twin PlatformPlatform
Builds virtual copies of physical systems so engineers can test operating conditions before changing the real thing.
OpenEye Scientific SoftwareProduct line
Molecular modeling and simulation software used in life-science research.
VLAB WorksBrand
Acquired technology that creates early virtual versions of hardware so embedded-software teams can begin sooner.
Cadence ConnectionsEcosystem
A partner network connecting Cadence tools with chip factories, computing providers, reusable blocks and design services.
Intel Foundry 14A EngagementCustomer program
A multiyear program adapting Cadence tools and chip blocks to Intel's future factory process; management expects most benefit in later years.
Unnamed Two-Nanometer Foundry IP EngagementCustomer program
Cadence's largest reusable-chip-block engagement with that unnamed factory customer as of April 2026; the customer was not Intel.
Unnamed Multiyear IP ContractCustomer program
A customer agreement disclosed in 2024 tied payments to delivery steps and carried work into 2025; later status was not disclosed.
Unallocated Customer CommitmentsCustomer program
Customers had made about $0.9B of June 2026 commitments they could not cancel, without yet choosing the Cadence products.
Arm Artisan Foundation IPProduct line
Acquired basic chip parts, memory-building tools and general-purpose connections that broaden the ready-made chip-block library.
Secure-IC Security IPProduct line
Acquired security technology now folded into Cadence's reusable chip-block portfolio.